# From ARM2 & ARM7500FE datasheets
# SWP=0, MRS_MSR=0 for ARMv2
# SWP=1, MRS_MSR=0 for ARMv2a
# SWP=1, MRS_MSR=1 for ARMv3
# CDP, LDC_STC, MRC_MCR should be null or expressions to reserve coprocessors

# 5.3 B, BL
(cond:4)101L(offset:24)	B_BL

# 5.4 Data processing
(cond:4)0000000S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	ADD_reg
(cond:4)0000000S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	ADD_rsr
(cond:4)0010000S(Rn:4)(Rd:4)(rotate:4)(imm:8)		ADD_imm
(cond:4)0000001S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	EOR_reg
(cond:4)0000001S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	EOR_rsr
(cond:4)0010001S(Rn:4)(Rd:4)(rotate:4)(imm:8)		EOR_imm
(cond:4)0000010S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	SUB_reg
(cond:4)0000010S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	SUB_rsr
(cond:4)0010010S(Rn:4)(Rd:4)(rotate:4)(imm:8)		SUB_imm
(cond:4)0000011S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	RSB_reg
(cond:4)0000011S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	RSB_rsr
(cond:4)0010011S(Rn:4)(Rd:4)(rotate:4)(imm:8)		RSB_imm
(cond:4)0000100S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	ADD_reg
(cond:4)0000100S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	ADD_rsr
(cond:4)0010100S(Rn:4)(Rd:4)(rotate:4)(imm:8)		ADD_imm
(cond:4)0000101S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	ADC_reg
(cond:4)0000101S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	ADC_rsr
(cond:4)0010101S(Rn:4)(Rd:4)(rotate:4)(imm:8)		ADC_imm
(cond:4)0000110S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	SBC_reg
(cond:4)0000110S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	SBC_rsr
(cond:4)0010110S(Rn:4)(Rd:4)(rotate:4)(imm:8)		SBC_imm
(cond:4)0000111S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	RSC_reg
(cond:4)0000111S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	RSC_rsr
(cond:4)0010111S(Rn:4)(Rd:4)(rotate:4)(imm:8)		RSC_imm
(cond:4)0001000S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	TST_reg
(cond:4)0001000S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	TST_rsr
(cond:4)0011000S(Rn:4)(Rd:4)(rotate:4)(imm:8)		TST_imm
(cond:4)0001001S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	TEQ_reg
(cond:4)0001001S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	TEQ_rsr
(cond:4)0011001S(Rn:4)(Rd:4)(rotate:4)(imm:8)		TEQ_imm
(cond:4)0001010S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	CMP_reg
(cond:4)0001010S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	CMP_rsr
(cond:4)0011010S(Rn:4)(Rd:4)(rotate:4)(imm:8)		CMP_imm
(cond:4)0001011S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	CMN_reg
(cond:4)0001011S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	CMN_rsr
(cond:4)0011011S(Rn:4)(Rd:4)(rotate:4)(imm:8)		CMN_imm
(cond:4)0001100S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	ORR_reg
(cond:4)0001100S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	ORR_rsr
(cond:4)0011100S(Rn:4)(Rd:4)(rotate:4)(imm:8)		ORR_imm
(cond:4)0001101S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	MOV_reg
(cond:4)0001101S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	MOV_rsr
(cond:4)0011101S(Rn:4)(Rd:4)(rotate:4)(imm:8)		MOV_imm
(cond:4)0001110S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	BIC_reg
(cond:4)0001110S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	BIC_rsr
(cond:4)0011110S(Rn:4)(Rd:4)(rotate:4)(imm:8)		BIC_imm
(cond:4)0001111S(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	MVN_reg
(cond:4)0001111S(Rn:4)(Rd:4)(Rs:4)0(type:2)1(Rm:4)	MVN_rsr
(cond:4)0011111S(Rn:4)(Rd:4)(rotate:4)(imm:8)		MVN_imm

# 5.5 PSR transfer
(cond:4)00010(Ps)001111(Rd:4)000000000000	{[MRS_MSR]}	{lnot(Ps)}	MRS in TST_reg
(cond:4)00010(Ps)001111(Rd:4)000000000000	{[MRS_MSR]}	{Ps}		MRS in CMP_reg
(cond:4)00010(Pd)101001111100000000(Rm:4)	{[MRS_MSR]}	{lnot(Pd)}	MSR_reg in TEQ_reg
(cond:4)00010(Pd)101001111100000000(Rm:4)	{[MRS_MSR]}	{Pd}		MSR_reg in CMN_reg
(cond:4)00010(Pd)101000111100000000(Rm:4)	{[MRS_MSR]}	{lnot(Pd)}	MSR_flg_reg in TEQ_reg
(cond:4)00010(Pd)101000111100000000(Rm:4)	{[MRS_MSR]}	{Pd}		MSR_flg_reg in CMN_reg
(cond:4)00110(Pd)1010001111(rotate:4)(imm:8)	{[MRS_MSR]}	{lnot(Pd)}	MSR_flg_imm in TEQ_imm
(cond:4)00110(Pd)1010001111(rotate:4)(imm:8)	{[MRS_MSR]}	{Pd}		MSR_flg_imm in CMN_imm

# 5.6 MUL, MLA
(cond:4)000000AS(Rd:4)(Rn:4)(Rs:4)1001(Rm:4)	MUL_MLA

# 5.7 LDR, STR
(cond:4)010PUBWL(Rn:4)(Rd:4)(imm:12)	LDR_STR_imm
(cond:4)011PUBWL(Rn:4)(Rd:4)(shift:5)(type:2)0(Rm:4)	LDR_STR_reg

# 5.8 LDM, STM
(cond:4)100PUSWL(Rn:4)(reglist:16)	LDM_STM

# 5.9 SWP, SWPB
(cond:4)00010B00(Rn:4)(Rd:4)00001001(Rm:4)	{[SWP]}	SWP_SWPB

# 5.10 SWI
(cond:4)1111(comment:24)	SWI

# 5.12 CDP
(cond:4)1110(CPOpc:4)(CRn:4)(CRd:4)(coproc:4)(CP:3)0(CRm:4)	[CDP]	CDP

# 5.13 LDC, STC
(cond:4)110PUNWL(Rn:4)(CRd:4)(coproc:4)(offset:8)	[LDC_STC]	LDC_STC

# 5.14 MRC, MCR
(cond:4)1110(CPOpc:3)L(CRn:4)(Rd:4)(coproc:4)(CP:3)1(CRm:4)	[MRC_MCR]	MRC_MCR

# 5.15 Undefined
(cond:4)011(:20)1(:4)	UNDEFINED

# Unpredictable
(cond:4)000(opcode:4)S(Rn:4)(Rd:4)(:4)1(x:2)1(Rm:4)	{lor(gt(opcode,1),x)} {lt(opcode,8)}	UNPREDICTABLE

# ARM2 data sheet lists the below as being UNDEFINED. ARMv3 docs don't list it as undefined, so treat it as UNPREDICTABLE if ARMv3, UNDEFINED if ARMv2/a.
(cond:4)0001aB(b:2)(Rn:4)(Rd:4)(c:4)1(d:2)1(Rm:4)	{[MRS_MSR]}	{lor(lor(a,b),lor(c,d))}	UNPREDICTABLE
(cond:4)0001aB(b:2)(Rn:4)(Rd:4)(c:4)1(d:2)1(Rm:4)	{[SWP]} {lnot([MRS_MSR])}	{lor(lor(a,b),lor(c,d))}	UNDEFINED
(cond:4)0001(:16)1(:2)1(:4)	{lnot([SWP])}	UNDEFINED1
